High-speed modular reduction device using multiples of module

Authors

  • Y.Zh. Aitkhozhayeva Satbayev University
  • S. Tynymbayev Almaty University of Power Engineering and Telecommunications named after G. Daukeeva
  • А.К. Mukasheva Almaty University of Power Engineering and Telecommunications named after G. Daukeeva
  • R. Berdybaev Almaty University of Power Engineering and Telecommunications named after G. Daukeeva
  • S. S. Adilbekkyzy Satbayev University

DOI:

https://doi.org/10.51301/vest.su.2021.i3.23

Keywords:

modulo reduction, modulus multiples, partial remainder formers

Abstract

A hardware implementation of a high-speed device for reducing numbers modulo is considered. We used a modified division algorithm with a shift of the dividend, where at each step n + 3 most significant bits of the dividend, and then the resulting remainders, participate. The shift of the reduced number at each step by three bits to the left towards the higher bits shifted and it makes it possible to speed up the process of reduction in modulus by reducing the number of modular reduction steps. The main unit of the device is a block of partial remainder formers (PRFs), which use subtraction of the P modulus and multiples of the P modulus.

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Published

2021-06-30

How to Cite

Айтхожаева , Е. ., Тынымбаев , С. . . . . . . ., Мукашева , А. . . . . . . ., Бердибаев , Р. ., & Әділбекқызы, С. . . . . . . . (2021). High-speed modular reduction device using multiples of module. Engineering Journal of Satbayev University, 143(3), 175–184. https://doi.org/10.51301/vest.su.2021.i3.23

Issue

Vol. 143 No. 3 (2021): Vestnik KazNRTU

Section

Technics and techology

License

Copyright (c) 2021 VESTNIK KAZNRTU

Creative Commons License

This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

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